1. Field of the Invention
The present invention relates to a semiconductor integrated circuit.
2. Description of the Related Art
An HVIC (High Voltage Integrated Circuit) has been well known as a semiconductor integrated circuit which drives and turns ON/OFF a switching power device constituting an upper arm of a bridge circuit for power reverse conversion (DC-to-AC conversion) of a PWM (Pulse Width Modulation) inverter etc. Recently, an element separation type HVIC which does not perform potential insulation by means of a transformer, a photocoupler, etc. but uses high voltage junction has been used in order to enhance a function to perform overcurrent detection and temperature detection when the switching power device is abnormal and in order to reduce the size and cost of a power supply system.
An HVIC which drives IGBTs (Insulated Gate Bipolar Transistors) used as switching power devices constituting a power conversion device such as an inverter will be used as an example to describe the connection configuration of the HVIC according to the related art. FIG. 7 is a circuit diagram showing the connection configuration of the high voltage integrated circuit. A power conversion device including a half-bridge circuit in which two switching power devices (IGBTs 114 and 115) are connected in series is shown in FIG. 7.
The power conversion device shown in FIG. 7 includes an HVIC, low voltage power supplies 112 and 113, IGBTs 114 and 115, and FWDs (Free Wheel Diodes) 116 and 117, an L-load (inductive load) 118, and a capacitor 119. In the power conversion device, the IGBT 115 serving as an upper arm of the half-bridge circuit and the IGBT 114 serving as a lower arm of the half-bridge circuit are turned ON alternately, so that high potential or low potential can be outputted alternately from a Vs terminal 111 serving as an output terminal. Thus, AC power can be supplied to (made to flow into) the L-load 118.
That is, the HVIC is a drive element which complementarily turns ON/OFF of the IGBT 115 as the upper arm of the half-bridge circuit and the IGBT 114 as the lower arm of the half-bridge circuit. For outputting high potential from the Vs terminal 111, the IGBTs 114 and 115 are operated by the HVIC so that the IGBT 115 as the upper arm can turn ON and the IGBT 114 as the lower arm can turn OFF. On the other hand, for outputting low potential from the Vs terminal 111, the IGBTs 114 and 115 are operated by the HVIC so that the IGBT 115 as the upper arm can turn OFF and the IGBT 114 as the lower arm can turn ON.
The HVIC includes a low side circuit (hereinafter referred to as low side control circuit: not shown) using potential of the GND (ground potential) as a reference. During the operating time of the HVIC, the low side control circuit outputs a gate signal for the IGBT 114 of the lower arm from an L-OUT. In addition, the HVIC outputs a gate signal for the IGBT 115 of the upper arm from an H-OUT using the potential of the Vs terminal 111 as a reference. The HVIC includes a level shift function (level shift circuit (level-up circuit and level-down circuit): not shown) for performing signal transmission between the low side control circuit and a high side circuit (hereinafter referred to as high side control circuit: not shown) in order to output the gate signal for the IGBT 115 of the upper arm from the H-OUT using the potential of the Vs terminal 111 as a reference.
The level-up circuit raises a logic level of an input signal inputted from an H-IN to generate a gate signal for the IGBT 115. The level-down circuit receives an abnormality signal 110 indicating abnormality such as overheating or overcurrent from the IGBT 115, forms an alarm signal based on the abnormality signal 110 and reduces the level of the alarm signal. The low side control circuit is connected to the H-IN. The low side control circuit outputs an input signal to the level-up circuit. The H-IN is an input terminal which receives an input of an input signal to be transmitted to a low side circuit which is disposed in a front stage of the level-up circuit.
An output terminal of the high side control circuit is connected to the H-OUT. The H-OUT is connected to a gate of the IGBT 115 of the upper arm. The H-OUT is an output terminal which supplies a gate signal to the IGBT 115. The low side control circuit is connected to an L-IN. The L-IN is an input terminal which receives an input of an input signal in order to supply a gate signal to the IGBT 114. The L-OUT is connected to a gate of the IGBT 114 of the lower arm which is disposed in a rear stage of the HVIC. The L-OUT is an output terminal which supplies a gate single to the IGBT 114.
An ALM-IN indicates an input of the abnormality signal 110. The abnormality signal 110 is inputted to a detection circuit (not shown) which forms an alarm signal based on the abnormality signal 110. The low side control circuit is connected to an ALM-OUT. The ALM-OUT is an output terminal which outputs an alarm signal whose level has been reduced by the level-down circuit. An H-VDD is a terminal which connects a high potential side of the low voltage power supply 113 using potential of a Vs as a reference. An L-VDD is a terminal which connects a high potential side of the low voltage power supply 112 using the potential of the GND as a reference.
The Vs is a terminal of intermediate potential (floating potential) fluctuating in the range of from potential of a high potential side Vss of a high voltage power supply (main circuit power supply) to the potential of the GND. The Vs is connected to the Vs terminal 111. The GND is a ground (earth) terminal. The low voltage power supply 112 is a low side drive power supply which is connected between the L-VDD of the HVIC and the GND. The low voltage power supply 113 is a high side drive power supply which is connected between the H-VDD and the Vs of the HVIC. An emitter of the IGBT 114 is connected to the GND serving as a low potential side of the high voltage power supply. A collector of the IGBT 114 is connected to an emitter of the IGBT 115. A collector of the IGBT 115 is connected to the high potential side Vss of the high voltage power supply.
In addition, the FWDs 116 and 117 are connected in reverse parallel to the IGBTs 114 and 115 respectively. A connection point between the collector of the IGBT 114 and the emitter of the IGBT 115 (that is, an output terminal of the half-bridge circuit) is connected to the Vs terminal 111. The Vs of the HVIC and the L-load 118 are connected to the Vs terminal 111. The L-load 118 is AC resistance (reactance) of, for example, a motor or an illuminator, etc. which operates using the bridge circuit configured to have a combination of the half-bridge circuit (IGBTs 114 and 115). The capacitor 119 is connected between the L-VDD and the GND.
Next, the level shift circuit (the level-up circuit and the level-down circuit) of the HVIC will be described. FIG. 8 is a circuit diagram showing the configuration of the level-up circuit. FIG. 9 is a circuit diagram showing the configuration of the level-down circuit. In each of FIGS. 8 and 9, a CMOS circuit which transmits an input signal to the level shift circuit and a CMOS circuit which transmits an output signal of the level shift circuit to a rear stage are shown as peripheral circuits of the level shift circuit. An H-IN, an H-OUT, an ALM-IN, an ALM-OUT, an H-VDD, an L-VDD, a Vs and the GND in FIGS. 8 and 9 correspond to the H-IN, the H-OUT, the ALM-IN, the ALM-OUT, the H-VDD, the L-VDD, the Vs and the GND shown in FIG. 7, respectively.
A level-up circuit 210 shown in FIG. 8 includes an n-channel type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 211, a level shift resistor 212, and a diode 213. The level-up circuit 210 is required when the IGBT 115 of the upper arm of the half-bridge circuit is an n-channel type. A drain of the n-channel MOSFET 211 is connected to one end of the level shift resistor 212 and a source of the n-channel MOSFET 211 is grounded. A body diode 214 which is connected in reverse parallel to the n-channel MOSFET 211 is built in the n-channel MOSFET 211. A connection point between the n-channel MOSFET 211 and the level shift resistor 212 is an output unit 215 of the level-up circuit 210.
The other end of the level shift resistor 212 is connected to the H-VDD. The diode 213 is connected in parallel to the level shift resistor 212. The diode 213 is disposed in order to prevent the level shift resistor 212 from being broken or to protectively clamp the CMOS circuit of a high side circuit 217 in a rear stage when the potential of the H-VDD is remarkably lower than the potential of the GND (when an excessively negative surge voltage (hereinafter referred to as negative surge voltage) is applied). In addition, the diode 213 has a function to prevent an excessive voltage from being applied to a gate of the CMOS circuit of the high side circuit 217 which will be described later, when the overvoltage is applied to the H-VDD during an ON-operation of the n-channel MOSFET 211. A Zener diode is typically often used as the diode 213.
A low side circuit 216 and the high side circuit 217 are provided as peripheral circuits of the level-up circuit 210. The low side circuit 216 is disposed within the low side control circuit and in a front stage of the level-up circuit 210. The high side circuit 217 is disposed within the high side control circuit and in a rear stage of the level-up circuit 210. Each of the low side circuit 216 and the high side circuit 217 has a CMOS circuit in which a p-channel MOSFET (PMOS) and an n-channel MOSFET (NMOS) are connected to complement each other. A gate of the CMOS circuit of the low side circuit 216 is connected to the H-IN to receive an input of an input signal transmitted from the outside. In the CMOS circuit of the low side circuit 216, a source of the p-channel MOSFET is connected to the L-VDD and a source of the n-channel MOSFET is grounded. Incidentally, each of the low side circuit 216 and the high side circuit 217 may have another transmission circuit than the CMOS circuit.
A connection point (output terminal) between the p-channel MOSFET and the n-channel MOSFET which constitute the CMOS circuit of the low side circuit 216 is connected to a gate of the n-channel MOSFET 211 to transmit an input signal to the level-up circuit 210. A gate of the CMOS circuit of the high side circuit 217 is connected to the output unit 215 of the level-up circuit 210 to receive the input of the input signal transmitted from the level-up circuit 210. In the CMOS circuit (hereinafter referred to as second CMOS circuit) of the high side circuit 217, a source of a p-channel MOSFET (hereinafter referred to as second p-channel MOSFET) 130a is connected to the H-VDD and a source of an n-channel MOSFET (hereinafter referred to as second n-channel MOSFET) 130b is connected to the Vs. A connection point between the second p-channel MOSFET 130a and the second n-channel MOSFET 130b which constitute the CMOS circuit of the high side circuit 217 is connected to the H-OUT to transmit an input signal to the HVIC.
In the level-up circuit 210 configured thus, an input signal inputted from the H-IN to the gate of the CMOS circuit of the low side circuit 216 is inputted to the gate of the n-channel MOSFET 211 of the level-up circuit 210 via the CMOS circuit of the low side circuit 216. Upon reception of the input of the input signal, the n-channel MOSFET 211 turns ON/OFF so that an output signal can be outputted from the output unit 215 of the level-up circuit 210 and inputted to the gate of the CMOS circuit of the high side circuit 217. Upon reception of the input of the input signal, the CMOS circuit of the high side circuit 217 turns ON/OFF so that an output signal (a signal whose level has been raised by the level-up circuit 210) of the CMOS circuit of the high side circuit 217 can be outputted from the H-OUT. The output signal is converted into a signal using the potential of the Vs terminal 111 as a reference, and inputted to the gate of the IGBT 115 of the upper arm. Upon reception of the input of the input signal, the IGBT 115 of the upper arm of the half-bridge circuit turns ON/OFF.
As shown in FIG. 9, the level-down circuit 220 includes a p-channel MOSFET 221, a level shift resistor 222, and a diode 223. A drain of the p-channel MOSFET 221 is connected to one end of the level shift resistor 222, and a source of the p-channel MOSFET 221 is connected to the H-VDD. A body diode 224 which is connected in reverse parallel to the p-channel MOSFET 221 is built in the p-channel MOSFET 221. A connection point between the p-channel MOSFET 221 and the level shift resistor 222 is an output unit 225 of the level-down circuit 220.
The other end of the level shift resistor 222 is grounded. The diode 223 is connected in parallel to the level shift resistor 222. The diode 223 has a function to prevent the level shift resistor 222 from being damaged when the potential of the H-VDD is remarkably lower than the potential of the GND. In addition, the diode 223 has a function to prevent an overvoltage from being applied to a gate of the CMOS circuit of a low side circuit 227 which will be described later, when the overvoltage is applied to the H-VDD during an ON-operation of the p-channel MOSFET 221.
A high side circuit 226 and the low side circuit 227 are provided as peripheral circuits of the level-down circuit 220. The high side circuit 226 is disposed within the high side control circuit and in a front stage of the level-down circuit 220. The low side circuit 227 is disposed within the low side control circuit and in a rear stage of the level-down circuit 220. Each of the high side circuit 226 and the low side circuit 227 has a CMOS circuit in which a p-channel MOSFET (PMOS) and an n-channel MOSFET (NMOS) are connected to complement each other. A gate of the CMOS circuit of the high side circuit 226 receives an input of an alarm signal formed based on an abnormality signal 110. In the CMOS circuit of the high side circuit 226, a source of the p-channel MOSFET is connected to the H-VDD and a source of the n-channel MOSFET is connected to the Vs. Incidentally, each of the low side circuit 227 and the high side circuit 226 may have another transmission circuit than the CMOS circuit.
A connection point (output terminal) between the p-channel MOSFET and the n-channel MOSFET which constitute the CMOS circuit of the high side circuit 226 is connected to a gate of the n-channel MOSFET 221 to transmit an input signal to the level-down circuit 220. A gate of the CMOS circuit of the low side circuit 227 is connected to the output 225 of the level-down circuit 220 to receive the input of the input signal transmitted from the level-down circuit 220. In the CMOS circuit of the low side circuit 227, a source of the p-channel MOSFET is connected to the L-VDD and a source of the n-channel MOSFET is grounded. A connection point between the p-channel MOSFET and the n-channel MOSFET which constitute the CMOS circuit of the low side circuit 227 is connected to the ALM-OUT to output an output signal to the outside from the ALM-OUT.
In the level-down circuit 220 configured thus, an alarm signal based on the abnormality signal 110 and inputted to the gate of the CMOS circuit of the high side circuit 226 is inputted to the gate of the p-channel MOSFET 221 of the level-down circuit 220 via the CMOS circuit of the high side circuit 226. Upon reception of the input of the input signal, the p-channel MOSFET 221 turns ON/OFF so that an output signal can be outputted from the output unit 225 of the level-down circuit 220 and inputted to the gate of the CMOS circuit of the low side circuit 227. Upon reception of the input of the input signal, the CMOS circuit of the low side circuit 227 turns ON/OFF so that an output signal (an alarm signal whose level has been reduced by the level-down circuit 220) of the CMOS circuit of the low side circuit 227 can be outputted from the ALM-OUT.
Next, the sectional structure of an HVIC according to the related art will be described with reference to FIGS. 7 to 10. FIG. 10 is a sectional view showing the structure of a high voltage integrated circuit (HVIC) according to the related art. FIG. 10 shows a logic portion of a low side control circuit 181, a logic portion of a high side control circuit 182, and a main part of an HVJT (High Voltage Junction Terminal region) 183, of respective constituent portions of a self-isolation type HVIC 180. An arrow continued from a right side of the sectional view illustrated in an upper side of FIG. 10 to a left side of the sectional view illustrated in a lower side of FIG. 10 indicates that the sectional view illustrated in the upper side is connected to the sectional view illustrated in the lower side to thereby form one p-type semiconductor substrate 101 (semiconductor chip) (the same rule also applies to FIGS. 1, 3 to 6 and 11).
As shown in FIG. 10, in the HVIC 180 according to related art, n− type well regions 102 and 104, an n type well region 103, and a p type well region 105 are respectively selectively provided in a front surface layer of a front surface of the p type semiconductor substrate 101 connected to the GND. The n− type well region 104 surrounds the circumference of the n type well region 103. The n− type well region 102 is provided outside the n− type well region 104 (on an opposite side to the side of the n type well region 103). The p type well region 105 is provided between the n− type well region 102 and the n− type well region 104.
A first CMOS circuit (a p-channel MOSFET (hereinafter referred to as first p-channel MOSFET) 120a and an n-channel MOSFET (hereinafter referred to as first n-channel MOSFET) 120b) which outputs a gate signal to the IGBT 114 of the lower arm of the half-bridge circuit is disposed as the low side control circuit 181 in the n− type well region 102. In addition, although not shown, the low side circuit 216 or 227 etc. serving as the peripheral circuit of the level shift circuit is disposed as the low side control circuit 181 in the n− type well region 102.
The level shift circuit, the high side circuit 217 or 226 serving as the peripheral circuit of the level shift circuit, etc. are disposed as the high side control circuit 182 in the n type well region 103. FIG. 10 shows a second CMOS circuit (a second p-channel MOSFET 130a and a second n-channel MOSFET 130b) which constitutes a logic part of the high side circuit 217. The high side circuit 217 is a peripheral circuit of the level-up circuit 210. The n-channel MOSFET 211 constituting the level-up circuit 210 is disposed to extend from the n type well region 103 over to the n− type well region 104 which serves as the HVJT 183 and the p type well region 105 which is adjacent to the n− type well region 104.
The n-channel MOSFET 211 constituting the level-up circuit 210 includes the n type well region 103, the n− type well region 104, the p type well region 105, n+ type regions 141, 144 and 161, a p+ type contact region 143, a gate electrode 148, a source electrode 145 and a drain electrode 162. The p type well region 105 serves as a base region. The n+ type region 144 serves as a source region. The n+ type region 161 serves as a drain region. The reference numerals 146 and 147 designate a pickup electrode and a p+ type contact region respectively. The reference numeral 142 designates a pickup electrode.
Specifically, the n+ type region 144 and the p+ type contact regions 143 and 147 are respectively selectively provided inside the p type well region 105. The n+ type region 141 is selectively provided inside the n type well region 103. The gate electrode 148 is provided, through a gate insulating film, on a front surface of a portion of the p type well region 105, which portion is interposed between the n+ type region 144 and the n+ type region 141 (an n type region including the n type well region 103 adjacent to the n+ type region 141 and the n− type well region 104). The source electrode 145 is adjacent to the n+ type region 144 and the p+ type contact region 143.
The source electrode 145 is connected to the GND. The drain electrode 162 is adjacent to the n+ type region 161. In addition, the drain electrode 162 is connected to the level shift resistor 212 (not shown in FIG. 10) through a front surface metal wiring (not shown) and electrically connected to the H-VDD through the level shift resistor 212. In addition, a connection portion between the drain electrode 162 and the level shift resistor 212 is the output portion 215 of the level-up circuit 210. An output from the output portion 215 is low in potential when the n-channel MOSFET for level shift is ON, and high in potential when the n-channel MOSFET for level shift is OFF. Therefore, the HVIC 180 can perform a level shift operation which is to transmit a signal between different reference potentials.
The reference numerals 122 to 125 designate an n+ type contact region, a p+ type source region, a p+ type drain region and a gate electrode of the first p-channel MOSFET 120a respectively. The reference numerals 121 and 126 to 129 designate a p type offset region, an n+ type drain region, an n+ type source region, a p+ type contact region and a gate electrode of the first n-channel MOSFET 120b respectively. The reference numerals 132 to 135 designate an n+ type contact region, a p+ type source region, a p+ type drain region and a gate electrode of the second p-channel MOSFET 130a respectively. The reference numerals 131 and 136 to 139 designate a p type offset region, an n+ type drain region, an n+ type source region, a p+ type contact region and a gate electrode of the second n-channel MOSFET 130b respectively. An H-OUT, an L-OUT, an H-VDD, an L-VDD, a Vs and the GND in FIG. 10 are terminals corresponding to the H-OUT, the L-OUT, the H-VDD, the L-VDD, the Vs and the GND shown in FIG. 7 respectively.
A bridge circuit constituted by a combination of half-bridge circuits each consisting of switching power devices (IGBTs 114 and 115) using such an HVIC 180 as a drive element can be used broadly in lots of fields such as a power supply for use in a large-capacity plasma display panel (PDP), a liquid crystal panel, etc., an inverter for a consumer electrical appliance such as an air conditioner or an illuminator, in addition to an inverter for motor control. The motor or illuminator etc. corresponds to the L-load 118 as described above. Therefore, the HVIC 180 is adversely influenced by a parasitic inductance component etc. caused by a wiring on a printed circuit board, a cable up to the L-load 118, etc.
Specifically, when the IGBT 115 of the upper arm is switched OFF or when the IGBT 114 of the lower arm is switched ON, the potential of the Vs terminal 111 (the reference potential of the high side circuit 217 or 226) or the potential of the H-VDD (the potential using the potential of the Vs terminal 111 as a reference) fluctuates to negative potential side with respect to the potential (0V) of the GND due to the adverse influence of the parasitic inductance component etc. A negative surge voltage VS0 which is negative in potential with respect to the potential of the GND is applied to the Vs terminal 111, for example, at a timing when the IGBT 115 of the upper arm is turned OFF. The negative surge voltage VS0 can be calculated by use of the following expression (1). In the following expression (1), the reference sign L0 designates an inductance value of the L-load 118; and the reference sign I designates a current value flowing into the IGBT 115.VS0=L0×dI/dt  (1)
When the negative surge voltage VS0 applied to the Vs terminal 111 is lower than [potential of GND−(Vspy+Vfd)], parasitic pn diodes 151 and 152 of the self-isolation type HVIC 180 (chip) start to be electrically conductive. The parasitic pn diode 151 includes the p type semiconductor substrate 101 and the n type well region 103. The parasitic pn diode 152 includes the p type well region 105 and the n− type well region 104. The reference sign Vspy designates a battery voltage between opposite ends of the low voltage power supply 113 serving as a high side drive power supply or between opposite ends of a not-shown bootstrap capacitor. The reference sign Vfd designates a forward voltage drop at the parasitic pn diode 151 or 152.
When the potential of the Vs terminal 111 is largely pulled to the negative side, an overcurrent flows into the HVIC 180 (chip). As a result, there is a fear that malfunction or latch-up occurring in the high side control circuit constituting the HVIC 180 may lead to failure or breakdown in the HVIC 180. The negative surge voltage VS0 applied to the Vs terminal 111 varies depending on the inductance value of the L-load 118 or the current flowing into the HVIC 180. The negative surge voltage VS0 is about −20 V to about −100 V and the application period thereof is about several hundred ns to about 1 μs.
As such an HVIC, proposed is a circuit (for example, see Japanese Patent No. 3346763) including a resistor which is connected in series to a parasitic diode in an HVIC chip and disposed between a substrate of the HVIC chip and a ground potential terminal so as to limit a current in a negative voltage spike (negative surge) flowing into the parasitic diode of the HVIC due to a negative voltage transient phenomenon at an output node in order to protect the HVIC which drives a half-bridge type power transistor in anticipation of an excessive negative swing (application of a negative surge voltage) at the output node.
In addition, as another HVIC, proposed is a device in which a diode is inserted between a drain electrode of a switching element belonging to a level shift circuit and a gate electrode of an MOS transistor belonging to an amplifier (CMOS circuit) so as to reduce an adverse influence of a negative voltage (reverse bias) applied beyond a rated breakdown voltage (for example, see JP-A-2001-25235). In JP-A-2001-25235, a current reversely flowing into the switching element can prevent the adverse influence on the operation of the amplifier.
In addition, as a further HVIC, proposed is a device in which a level shift resistor, a current limiting resistor and a switching element (whose drain is on a high potential side) constituting a level-up circuit are connected in series between the high potential side and a low potential (ground potential) side of a high voltage power supply in the named order from the high potential side of the high voltage power supply, and an area between the level shift resistor and the current limiting resistor is set as an output of the level-up circuit (for example, see JP-A-2008-301160). In JP-A-2008-301160, the current limiting resistor is connected to a current path between a high potential side (H-VDD) and a low potential side (GND) of a low voltage power supply of the level shift circuit using the potential of a Vs terminal as a reference. Thus, a body diode of an n-channel MOSFET constituting the level-up circuit and a parasitic pn diode itself of the HVIC can be prevented from being breakdown due to an overcurrent, or any small current capacity portion of the level shift circuit can be prevented from being breakdown due to an overcurrent.
In addition, the following device is proposed as a further HVIC. An n type well region where a high side circuit is provided is provided in a front surface layer of a p type semiconductor substrate. A p type offset region for providing an n-channel MOSFET of a CMOS circuit constituting a logic portion of the high side circuit is provided inside the n type well region and a p+ type impurity region which is as high in potential as a Vs is provided adjacently to the p type offset region. Further, an n+ type impurity region and a p+ type impurity region which are as high in potential as an H-VDD are provided within the n type well region where the high side circuit is provided and in the periphery of the CMOS circuit constituting the logic portion of the high side circuit (for example, see Japanese Patent No. 5072043).
In Japanese Patent No. 5072043, the n+ type impurity region and the p+ type impurity region are provided in the n type well region constituting the high side circuit and these impurity regions are fixed to be as high in potential as the H-VDD or the Vs. Accordingly, a hole current flowing into the n type well region from the region which is as high in potential as the GND is absorbed before flowing into a p type well region. Thus, a parasitic operation caused by application of a negative surge voltage in the logic portion of the high side circuit using the potential of the Vs terminal as a reference can be prevented to avoid latch-up in a parasitic thyristor.
In addition, the following device is proposed as a further HVIC. An n type region serving as a high side floating potential region, an n− type region serving as a high voltage junction terminal region, and an n type region serving as a low side power supply (L-VDD) potential region are provided in a front surface layer of a p type semiconductor substrate and a low side circuit is disposed in the low side power supply potential region. A universal contact region which forms an ohmic contact (an electric contact portion) with a pickup electrode is provided in the high voltage junction terminal region. The universal contact region has a configuration in which p+ type regions and n+ type regions are repeated alternately and arranged to be adjacent to each other along the front surface of the p type semiconductor substrate (for example, see Japanese Patent No. 5099282).
Japanese Patent No. 5099282 discloses that a pickup between the high potential n− type region forming the HVJT (High Voltage Junction Terminal region) and the GND potential p type region is formed as a universal electrode in order to enhance an effect of extracting minority carriers toward the high side circuit or the low side circuit due to the parasitic diode operated when a negative surge voltage is applied. Thus, according to Japanese Patent No. 5099282, it is possible to reduce the amount of carriers flowing into the low side control circuit and prevent malfunction or breakdown due to latch-up in the logic portion of the low side control circuit when the negative surge voltage is applied to the HVIC.
However, the aforementioned HVIC according to the related art has the following problems. Description will be made by way of example in the case where the high potential side Vss of the high voltage power supply (main circuit power supply) is about 1,200 V and the potential of the H-VDD of the HVIC is higher than the potential of the Vs by about 20 V in the power conversion device in which the switching power devices (IGBTs 114 and 115) and the HVIC are connected to each other, as shown in FIG. 7. When the IGBT 115 of the upper arm of the half-bridge circuit turns ON and the IGBT 114 of the lower arm of the half-bridge circuit turns OFF, current flows toward the L-load 118 from the IGBT 115 of the upper arm.
When the IGBT 115 of the upper arm turns OFF in this state, the current flows from the GND into the L-load 118 via the FWD 116 which is connected in parallel to the IGBT 114 of the lower arm because the L-load 118 intends to maintain the current flowing into the power conversion device (the current phase with respect to the AC voltage delays due to the L-load 118). Thus, the potential of the Vs terminal 111 becomes lower than the potential of the GND, for example, to be about −100V. When the potential of the Vs terminal 111 reaches about −100V, the potential of the H-VDD is higher than the potential of the Vs by about 20V as described above. Accordingly, the potential of the H-VDD is about −80V (=−100V+20V).
In the structure of the HVIC 180 according to the related art as shown in FIG. 10, the p type semiconductor substrate 101 and the p type well region 105 are as high in potential as the GND. Therefore, when the potential of the Vs terminal 111 decreases until the n type well region 103 and the n− type well region 104 constituting the CMOS circuit of the logic portion of the high side circuit 217 in the periphery of the level-up circuit 210 become lower in potential than the GND, the parasitic pn diode 151 or 152 is brought into a forward bias so that a large current flows. Due to the large current, the high side circuit 217 or 226 or the low side circuit 216 or 227 in the HVIC 180 malfunctions or breakdown due to latch-up.
As to the malfunction or the breakdown caused by the parasitic operation, a resistor for limiting a current is connected between the substrate and the ground terminal to suppress the amount of the current in Japanese Patent No. 3346763, which, however, has no suggestion about whether the resistor may be connected to any other place. In addition, since the resistor is formed as a polysilicon layer, there is a possibility for the polysilicon layer constituting the resistor may be thermally melted and breakdown by an overcurrent when a large pulse current (several ampere (A)−tens of ampere (A)) caused by a negative surge voltage flows into the parasitic diode between the Vs terminal and the ground terminal transiently.
JP-A-2001-25235 has no description about the body diode of the MOSFET constituting the level shift circuit or the resistor or layout for limiting the current of the parasitic pn diode of the HVIC when the potential of the H-VDD becomes negative due to the L-load. JP-A-2008-301160 has no description about how to prevent malfunction (incorrect inversion) caused by a parasitic operation of the CMOS circuit constituting the logic portion of the high side control circuit using the potential of the Vs terminal as a reference or the CMOS circuit constituting the logic portion of the low side control circuit using the potential of the GND as a reference. Japanese Patent No. 5072043 has no description about how to prevent malfunction caused by a parasitic operation of the CMOS circuit constituting the logic portion of the low side control circuit portion.
In addition, in Japanese Patent No. 5099282, the present inventor has mentioned about reduction of the amount of minority carriers injected into the high side control circuit or the low side control circuit portion. It is because, when the minority carriers are injected into the high side control circuit and/or the low side control circuit portion, in the HVIC, a malfunctions and/or breakdown due to latch-up occur caused by a parasitic operation of the CMOS circuit constituting the logic portion of the high side control circuit and/or the low side control circuit. Malfunction caused by a parasitic operation of one of the CMOS circuits constituting the logic portions of the low side control circuit 181 and the high side control circuit 182 of the HVIC 180 according to the related art will be described below.
FIG. 11 is an explanatory view showing behavior of electrons and holes when a negative surge voltage is applied to the high voltage integrated circuit in FIG. 10 via the H-VDD. The configuration of the level-up circuit (the n-channel MOSFET 211 in FIG. 8) is not shown in FIG. 11. When the negative surge voltage is applied to the H-VDD via the Vs terminal 111 (see FIG. 7), a forward current flows into the parasitic pn diode 152. On this occasion, minority carriers (electrons) are injected from the n type well region 104 serving as a cathode region of the parasitic pn diode 152 into the p type well region 105 serving as an anode region of the parasitic pn diode 152.
The electrons injected into the p type well region 105 are not substantially extracted from the p+ type contact region 143 provided inside the p type well region 105 but flow into the n− type well region 102 adjacent to the outer side of the p type well region 105 (the outer circumferential side of the chip), and flow toward the n+ type contact region 122 inside the n− type well region 102. The n+ type contact region 122 is, for example, about 15V higher in potential than the n− type well region 102. In that process, a voltage drop occurs in a parasitic resistor 153 present inside the n− type well region 102 in which the CMOS circuit (the first p-channel MOSFET 120a and the first n-channel MOSFET 120b) constituting the logic portion of the low side control circuit 181 is provided.
The potential of the n− type well region 102 in the vicinity of the p+ type drain region 124 of the first p-channel MOSFET 120a is pulled down by the voltage drop of the parasitic resistor 153. As a result, a parasitic pnp bipolar transistor 154 turns ON. In the parasitic pnp bipolar transistor 154, the p+ type drain region 124 of the first p-channel MOSFET 120a constituting the logic portion in the low side control circuit 181 serves as an emitter, the n− type well region 102 serves as a base, and the p type semiconductor substrate 101 serves as a collector. Therefore, there is a fear that malfunction such as inversion of the output logic of the L-OUT etc. may be caused or breakdown due to latch-up in the low side control circuit 181 may be caused.
On the other hand, minority carriers (holes) are injected from the p type well region 105 into the n− type well region 104. The holes having entered the n− type well region 104 flow into the n type well region 103, and further flow into the p+ type source region 133 and the p+ type drain region 134 of the second p-channel MOSFET 130a constituting the logic portion of the high side control circuit 182, or further flow into the p type offset region 131 in which the second n-channel MOSFET 130b is provided. Thus, a parasitic npn transistor (not shown) turns ON. In the parasitic npn transistor, the n+ type source region 137 of the second n-channel MOSFET 130b serves as an emitter, the p type offset region 131 serves as a base, and the n type well region 103 serves as a collector. Therefore, there is a fear that malfunction or breakdown due to latch-up may occur in the logic portion of the high side control circuit 182.